Semiconductor device

ABSTRACT

A semiconductor device having a plurality of chips is reduced in size. In HSOP(semiconductor device) for driving a three-phase motor, a first semiconductor chip including a pMISFET and a second semiconductor chip including an nMISFET are mounted over each of a first tab, second tab, and third tab. The drains of the PMISFET and nMISFET over each tab are electrically connected with each other. Thus, two of six MISFETs can be placed over each of three tabs divided in correspondence with the number of phases of the motor, and they can be packaged in one in a compact manner. As a result, the size of the HSOP for driving a three-phase motor, having a plurality of chips can be reduced.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority from Japanese patent applicationNo. 2005-191449 filed on Jun. 30, 2005, the content of which is herebyincorporated by reference into this application

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and inparticular to a technique effectively applicable to a semiconductordevice having power MISFETs

(Metal Insulator Semiconductor Field Effect Transistors).

For example, Patent Documents 1 and 2 disclose semiconductor devices fordriving a three-phase motor.

For example, Patent Documents 3 and 4 disclose semiconductor devices forDC-DC converter.

For example, Patent Document 5 discloses a processing method for HSOP.

[Patent Document 1] Japanese Unexamined Patent Publication No.2004-273749 (FIG. 1)

[Patent Document 2] Japanese Unexamined Patent Publication No.2003-197862 (FIG. 3)

[Patent Document 3] Japanese Unexamined Patent Publication No.2003-124436 (FIG. 5)

[Patent Document 4] Japanese Unexamined Patent Publication No.2003-332518 (FIG. 17)

[Patent Document 5] Japanese Unexamined Patent Publication No.2002-110882 (FIG. 1)

For example, when a circuit for driving a vehicle-mounted motor or anyother like motor is constructed, a plurality of MOSFETs (Metal OxideSemiconductor Field Effect Transistors) are used for this purpose. Theplurality of MOSFETs are independently formed in a plurality ofpackages. The circuit for driving a motor is constructed by mountingthese plurality of packages over a mounting board.

In this case, a problem arises because a plurality of semiconductordevices are mounted. A footprint is increased, and downsizing isinfeasible.

Consequently, the present inventors considered multi (plural) chippackages (semiconductor devices) of high heat radiation type which allowfootprints to be reduced.

A DC-DC converter having two MOSFETs (semiconductor chips) will be takenas an example. In cases where the DC-DC converter has two semiconductorchips mounted over a tab and two MOSFETs are nMOSFET and pMOSFET, adrain can be shared between them. Therefore, the tab need not bedivided, and the DC-DC converter is of such construction that twosemiconductor chips are mounted over one tab.

In cases where two MOSFETs are both nMOSFET in a DC-DC converter, adrain cannot be shared between them. Therefore, it is required to dividea tab into one for the high-side semiconductor chip of one nMOSFET andone for the low-side semiconductor chip of the other nMOSFET. Thus, theDC-DC converter is of such construction that a semiconductor chipcontaining an nMOSFET is mounted over each of the two divided tabs.(Refer to Patent Document 3.)

That is, in a DC-DC converter having two MOSFETs (semiconductor chips),a tab is so constructed that it is not divided as in the former of theabove examples or so constructed that it is divided into two as in thelatter.

In the technology disclosed in Patent Document 1 (Japanese UnexaminedPatent Publication No. 2004-273749) a wire is connected to a frame.Therefore, the following problem arises: it is required to ensure areasfor wire connection in frames, and this imposes limitation on chip size.

In addition, the following problem can also arise: since wires arebonded astride frames, the switching noise of a low-side transistorelement adversely affects a high-side transistor element via theinductance of a wire. As a result, the high-side transistor element canbe caused to malfunction.

SUMMARY OF THE INVENTION

An advantage of the invention is to provide a technique that enablesdownsizing of a semiconductor device having a plurality of chips.

Another advantage of the invention is to provide a technique thatenables the enhancement of the heat radiating property of asemiconductor device having a plurality of chips.

The above and further advantages and novel features of the inventionwill be apparent from the description of this specification and theaccompanying drawings.

The following is a brief description of the gist of the representativeelements of the invention laid open in this application.

The invention includes: a semiconductor chip including a pMISFET and asemiconductor chip including an nMISFET respectively mounted over first,second, and third tabs; a plurality of leads electrically connected withthe individual semiconductor chips; and a sealing portion that seals thefirst, second, and third tabs and the semiconductor chips. The drains ofthe PMISFET and nMISFET mounted over each of the first, second, andthird tabs are electrically connected with each other.

Also, the invention includes: a semiconductor chip including a pMISFETand a semiconductor chip including an nMISFET respectively mounted overfirst and second tabs; a plurality of leads electrically connected withthe individual semiconductor chips; and a sealing portion that seals thefirst and second tabs and the semiconductor chips. The drains of thepMISFET and nMISFET mounted over each of the first and second tabs areelectrically connected with each other.

Further, the invention includes: first, second, third, and fourth tabs;semiconductor chips including a pMISFET respectively mounted over firstand second tabs; semiconductor chips including an nMISFET respectivelymounted over third and fourth tabs; a plurality of leads electricallyconnected with each semiconductor chip; and a sealing portion that sealsthe first, second, third, and fourth tabs and the semiconductor chips.

The following is a brief description of the gist of the effects obtainedby the representative elements of the invention laid open in thisapplication.

In a semiconductor device for driving a three-phase motor, asemiconductor chip including a PMISFET and a semiconductor chipincluding an nMISFET are mounted over each of first, second, and thirdtabs. The drains of the PMISFET and nMISFET over each tab areelectrically connected with each other. This makes it possible to placetwo of six MISFETs over each of three tabs divided in accordance withthe number of phases of the motor and package them in one in a compactmanner. As a result, the semiconductor device for driving a three-phasemotor, having a plurality of chips can be reduced in size. The backsides of the first, second, and third tabs are exposed from the sealingportion, and the thickness of each tab is greater than the thickness ofleads. Therefore, the heat radiating property of the tabs can beenhanced. As a result, the heat radiating property of the semiconductordevice for driving a three-phase motor, having a plurality of chips canbe enhanced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view illustrating an example of the construction of asemiconductor device (for driving a three-phase motor) in a firstembodiment of the invention as viewed through its sealing portion.

FIG. 2 is an equivalent circuit diagram illustrating an example ofcircuitry for driving a three-phase motor, using the semiconductordevice illustrated in FIG. 1.

FIG. 3 is an equivalent circuit diagram illustrating an example ofcircuitry in which a semiconductor device in the first embodiment of theinvention is applied to HSOP.

FIG. 4 is a circuitry diagram illustrating an example of the operationof a drive circuit in which n and pMISFETs are incorporated togetherwith respect to the semiconductor device illustrated in FIG. 1.

FIG. 5 is a circuitry diagram illustrating the operation of a drivecircuit in which only nMISFETs are incorporated with respect to asemiconductor device in a comparative example.

FIG. 6 is a perspective view illustrating an example of the constructionof the semiconductor device illustrated in FIG. 1.

FIG. 7 is a perspective view illustrating an example of the constructionof the back side of the semiconductor device illustrated in FIG. 1.

FIG. 8 is a sectional view illustrating an example of the constructionof the semiconductor device illustrated in FIG. 1.

FIG. 9 is a sectional view illustrating an example of the constructionof a semiconductor chip incorporated in the semiconductor deviceillustrated in FIG. 1.

FIG. 10 is a plan view illustrating an example of the construction ofthe semiconductor chip illustrated in FIG. 9.

FIG. 11 is a partial plan view illustrating an example of theconstruction of a lead frame used in the assembly of the semiconductordevice illustrated in FIG. 1.

FIG. 12 is a sectional view illustrating the construction of the leadframe illustrated in FIG. 11, taken along the line A-A of FIG. 11.

FIG. 13 is a partial plan view illustrating the construction of aprincipal part of the lead frame illustrated in FIG. 11.

FIG. 14 is a sectional view illustrating the construction of the leadframe illustrated in FIG. 13, taken along the line B-B of FIG. 13.

FIG. 15 is a partial plan view illustrating the construction of a leadframe in a modification to the first embodiment of the invention.

FIG. 16 is a sectional view illustrating the construction of the leadframe illustrated in FIG. 15, taken along the line A-A of FIG. 15.

FIG. 17 is a partial sectional view illustrating an example of theconstruction of the semiconductor device illustrated in FIG. 1 afterwire bonding in its assembly.

FIG. 18 is a thermal resistance data diagram illustrating an example ofthe actual measurement data about thermal resistance due to the platethickness of a tab in a semiconductor device in the first embodiment ofthe invention.

FIG. 19 is a plan view illustrating an example of the construction of asemiconductor device (with its tab divided into two and for driving asingle-phase motor) in a second embodiment of the invention as viewedthrough its sealing portion.

FIG. 20 is a rear view illustrating an example of the construction ofthe back side of the semiconductor device illustrated in FIG. 19, asapplied to HSOP.

FIG. 21 is an equivalent circuit diagram illustrating an example of thecircuitry for driving a single-phase motor in the semiconductor deviceillustrated in FIG. 19.

FIG. 22 is a plan view illustrating an example of the construction of asemiconductor device (with its tab divided into four and for driving asingle-phase motor) in a third embodiment of the invention as viewedthrough its sealing portion.

FIG. 23 is a rear view illustrating an example of the construction ofthe back side of the semiconductor device illustrated in FIG. 22, asapplied to HSOP.

FIG. 24 is an equivalent circuit diagram illustrating an example of thecircuitry for driving a single-phase motor in the semiconductor deviceillustrated in FIG. 22.

FIG. 25 is a plan view illustrating the construction of a semiconductordevice (HSOP mounted only with nMISFETs) in a comparative example asviewed through its sealing portion.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following description of embodiments, an identical or similarportion will not be repeatedly described as a rule unless thedescription is especially required.

In the following description of embodiments, one embodiment will bedivided into plural sections or embodiments if necessary forconvenience. However, they are not independent of one another but are insuch relation that one is a modification to or the details,supplementary explanation, or the like of part or all of another.

In cases where a number of elements (including a number of pieces,numeric value, quantity, range, and the like) is cited in the followingdescription of embodiments, the invention is not limited to thatspecific number. Any number greater or less than that specific number isacceptable. However, this does not apply when otherwise stated, when theinvention is obviously limited to that specific number according to theprinciple, or in other like cases.

Hereafter, detailed description will be given to embodiments of theinvention with reference to the drawings. In all the drawings for theexplanation of embodiments, members having the same functions will bemarked with the same reference numerals, and the repetitive descriptionof them will be omitted.

First Embodiment

FIG. 1 is a plan view illustrating an example of the construction of asemiconductor device (for driving a three-phase motor) in a firstembodiment of the invention as viewed through its sealing portion; FIG.2 is an equivalent circuit diagram illustrating an example of circuitryfor driving a three-phase motor, using the semiconductor deviceillustrated in FIG. 1; FIG. 3 is an equivalent circuit diagramillustrating an example of circuitry in which a semiconductor device inthe first embodiment of the invention is applied to HSOP; and FIG. 4 isa circuitry diagram illustrating an example of the operation of a drivecircuit in which n and PMISFET are incorporated together with respect tothe semiconductor device illustrated in FIG. 1. FIG. 5 is a circuitrydiagram illustrating the operation of a drive circuit in which onlynMISFETs are incorporated with respect to a semiconductor device in acomparative example; FIG. 6 is a perspective view illustrating anexample of the construction of the semiconductor device illustrated inFIG. 1; FIG. 7 is a perspective view illustrating an example of theconstruction of the back side of the semiconductor device illustrated inFIG. 1; FIG. 8 is a sectional view illustrating an example of theconstruction of the semiconductor device illustrated in FIG. 1; FIG. 9is a sectional view illustrating an example of the construction of asemiconductor chip incorporated in the semiconductor device illustratedin FIG. 1; and FIG. 10 is a plan view illustrating an example of theconstruction of the semiconductor chip illustrated in FIG. 9. FIG. 11 isa partial plan view illustrating an example of the construction of alead frame used in the assembly of the semiconductor device illustratedin FIG. 1; FIG. 12 is a sectional view illustrating the construction ofthe lead frame illustrated in FIG. 11, taken along the line A-A of FIG.11; FIG. 13 is a partial plan view illustrating the construction of aprincipal part of the lead frame illustrated in FIG. 11; and FIG. 14 isa sectional view illustrating the construction of the lead frameillustrated in FIG. 13, taken along the line B-B of FIG. 13.

FIG. 15 is a partial plan view illustrating the construction of a leadframe in a modification to the first embodiment of the invention; FIG.16 is a sectional view illustrating the construction of the lead frameillustrated in FIG. 15, taken along the line A-A of FIG. 15; FIG. 17 isa partial sectional view illustrating an example of the construction ofthe semiconductor device illustrated in FIG. 1 after wire bonding in itsassembly; and FIG. 18 is a thermal resistance data diagram illustratingan example of the actual measurement data about thermal resistance dueto the plate thickness of a tab in a semiconductor device in the firstembodiment of the invention.

The semiconductor device in the first embodiment is a semiconductorpackage for driving a three-phase motor. It is of multichip structureand has a plurality of semiconductor chips each having a MISFETincorporated in it.

The above semiconductor device is of high heat radiation type. In thedescription of the first embodiment, the HSOP (Heat Sink Small OutlinePackage) 46 illustrated in FIG. 1 will be taken as an example of theabove semiconductor device. Such a semiconductor device is used forin-vehicle applications, for example. However, its applications are notlimited to in-vehicle applications but it may be used to drive a commonmotor or the like.

The HSOP 46 is a semiconductor package for driving a three-phase motor.As illustrated in FIG. 2, therefore, it has three sets of circuits fordriving, each set composed of a p-channel MISFET (hereafter, referred toas “pMISFET”) 32 and an n-channel MISFET (hereafter, referred to as“nMISFET”) 33, in correspondence with three phases. It drives a motor 40in three phases by power supply 42 and a signal from a driver IC(Integrated Circuit) 41.

As illustrated in FIG. 3, the HSOP 46 has three pMISFETs 32 on thehigh-supply voltage side (high side) and three nMISFETs 33 on thelow-supply voltage side (low side). It drives the motor 40 in threephases by the six MISFETs in total. That is, it has three sets ofcircuits for driving, each set composed of a pMISFET 32 and an nMISFET33. It causes signals in phases U, V, and W to be individually outputtedfrom drains by the respective circuits, and thus drives the motor 40 inthree phases. Therefore, the HSOP 46 is a semiconductor device in whichp and nMISFETs are incorporated together.

The pMISFETs 32 and nMISFETs 33 are those with low breakdown voltage,and their voltage between source and drain is lower than 100V(VDSS<100V).

The HSOP 46 in the first embodiment has three tabs (first tab 34, secondtab 35, and third tab 36) divided in correspondence with the number ofphases (three phases) of the motor 40 as illustrated in FIG. 1. One setof a PMISFET 32 and an nMISFET 33 is mounted over each tab. One set of afirst semiconductor chip 30 including a PMISFET 32 and a secondsemiconductor chip 31 including an nMISFET 33 is mounted over each ofthe main surfaces 34a, 35a, and 36a of the first tab 34, second tab 35,and third tab 36. (Refer to FIG. 14.)

The three first semiconductor chips 30 each including a PMISFET 32 areplaced on the high side and the three second semiconductor chips 31 eachincluding an nMISFET 33 placed on the low side.

The source pads 30 c formed over the main surfaces 30 a of the firstsemiconductor chips 30 are electrically connected with correspondingleads 37 b for source through conductive wires 39. The gate pads 30 dsimilarly formed are electrically connected with corresponding leads 37a for gate through conductive wire 39. As illustrated in FIG. 8, theback sides 30 b of the first semiconductor chips 30 form drain pads 30e. These drain pads 30 e are electrically connected with tabs throughsolder 43. Further, leads 37 c for drain (some of the leads 37) and thetabs are integrally joined with each other.

Similarly, the source pads 31 c formed over the main surfaces 31 a ofthe second semiconductor chips 31 are electrically connected withcorresponding leads 37 b for source through conductive wires 39. Thegate pads 31 d similarly formed are electrically connected withcorresponding leads 37 a for gate through conductive wires 39. Asillustrated in FIG. 8, the back sides 31 b of the second semiconductorchips 31 form drain pads 31 e. These drain pads 31 e are electricallyconnected with tabs through solder 43. Further, the tabs and leads 37 cfor drain (some of the leads 37) are integrally joined with each other.

Therefore, the first semiconductor chip 30 and second semiconductor chip31 over the first tab 34 share a drain electrode between them over thetab; the first semiconductor chip 30 and second semiconductor chip 31over the second tab 35 share a drain electrode between them over thetab; and the first semiconductor chip 30 and second semiconductor chip31 over the third tab 36 share a drain electrode between them over thetab.

That is, the first tab 34, second tab 35, and third tab 36 arerespectively electrically connected with the drains of a PMISFET 32 andan nMISFET 33. The drains of the pMISFETs 32 and the nMISFETs 33 areelectrically connected with each other through each of the first tab 34,second tab 35, and third tab 36.

However, the drain electrodes of MISFETs are not electricallyshort-circuited between phases because a tab is divided into three incorrespondence with the number of phases of the motor 40.

FIG. 1 illustrates the disposition (G, S, D) of the plurality of leads37 composed of leads 37 a for gate, leads 37 b for source, and leads 37c for drain as an example. However, the disposition of the leads is notlimited to that illustrated in FIG. 1.

A comparison will be made between a drive circuit with p and nMISFETsincorporated together and a high-side drive circuit with nMISFETs onlyincorporated with reference to FIG. 4 (first embodiment) and FIG. 5(comparative example).

FIG. 4 illustrates an example of a drive circuit with p and nMISFETsincorporated together, adopted in the HSOP 46 in the first embodiment.FIG. 5 illustrates a high-side drive circuit with nMISFETs onlyincorporated as a comparative example.

As illustrated FIG. 4, the PMISFET 32 can operate as the result of thefollowing: Q1 operates and thus the voltage at point A (gate) becomeslower than the potential at point B (source). That is, the drive circuitwith p and nMISFETs incorporated together, illustrated in FIG. 4, can beoperated with very simple circuitry.

To operate the nMISFET 33 in the drive circuit in FIG. 5 as acomparative example, the voltage at point D (gate) must be higher thanthe potential at point C (source). Since point C is at substantially thesame potential as +B during operation, however, a driver IC 101 providedwith a booster circuit for making the potential at point D higher thanthat at point C. Therefore, a drive circuit with nMISFETs onlyincorporated inevitably uses IC, and this complicates the circuit.

Therefore, the drive circuit with p and nMISFETs incorporated together,adopted in the first embodiment can be constructed with more simplecircuitry as compared with the drive circuit with nMISFETs onlyincorporated as a comparative example. Therefore, the circuit with p andnMISFETs incorporated together allows footprints to be reduced.

Description will be given to the details of the construction of the HSOP46 in the first embodiment. It has the first tab 34, second tab 35, andthird tab 36, which are tabs divided into three in correspondence withthree phases. As illustrated in FIG. 1, a first semiconductor chip 30including a PMISFET 32 and a second semiconductor chip 31 including annMISFET 33 are mounted over each tab.

The individual semiconductor chips are electrically connected withcorresponding leads 37 through wires 39. More specific description willbe given. The gate pads 30 d of the first semiconductor chips 30 and thegate pads 31 d of the second semiconductor chips 31 are electricallyconnected with respective corresponding leads 37 a for gate throughwires 39. The source pads 30 c of the first semiconductor chips 30 andthe source pads 31 c of the second semiconductor chips 31 areelectrically connected with respective corresponding leads 37 b forsource through wires 39.

The drain pads 30 e of the first semiconductor chips 30 and the drainpads 31 e of the second semiconductor chips 31 are electricallyconnected with respective tabs through solder 43.

Parts of the first tab 34, second tab 35, third tab 36, and a pluralityof leads 37, the first semiconductor chips 30, and the secondsemiconductor chips 31 are plastic molded with a sealing portion 44formed of sealing resin.

As illustrated in FIG. 7, the respective back sides 34 b, 35 b, and 36 bof the first tab 34, second tab 35, and third tab 36 are exposed at theunderside of the sealing portion 44. As illustrated in FIG. 8 and FIG.14, the respective thickness of the first tab 34, second tab 35, andthird tab 36 is larger than the thickness of the leads 37 (twice tothree times or so).

As mentioned above, parts (back sides 34 b, 35 b, and 36 b) of theindividual tabs that also function as drain terminals are exposed at theunderside of the sealing portion 44. Each tab is so formed that it isthicker than the leads 37. As a result, each tab can be provided with aheat sink function to enhance the heat radiating property of the HSOP46.

FIG. 18 illustrates an example of the relation between time and thermalresistance with various tab thicknesses taken as a parameter by actualmeasurement data. In case of (B) in which the tab is thick (t=1.3 mm) orin case of HSOP (t=1.26 mm), the thermal resistance is lower than incase of (A) in which the tab is thin (t=0.5 mm). Therefore, the heatradiating property of the HSOP 46 can be enhanced by adopting a thicktab (heat sink). An example of (A) is a surface mount MOSFET, and anexample of (B) is a large surface mount MOSFET.

As illustrated in FIG. 8, the wire bonding faces 37d of the individualplural leads 37 are disposed that they are farther from the respectivetabs than the tabs' main surfaces 34 a, 35 a, and 36 a on the mainsurface side. More specific description will be given. Some of the leads37 (the leads 37 c for drain) are stepped, and thus the wire bondingfaces 37 d of the leads 37 are so disposed that they are higher than themain surfaces 34 a, 35 a, and 36 a of the individual tabs.

Therefore, the wires 39 can be prevented from being brought into contactwith an edge of the main surface of a chip. Thus, the wires 39 can beprevented from being short-circuited to a first semiconductor chip 30 ora second semiconductor chip 31.

A plurality of outer leads 37 e of the plural leads 37 protruding fromside faces of the sealing portion 44 are bent into gull wing shape asillustrated in FIG. 6 and FIG. 8. The surfaces of the outer leads 37 eand the back sides 34 b, 35 b, and 36 b of the tabs are coated withsolder plating 45 as outer plating.

The first semiconductor chips 30 and the second semiconductor chips 31are formed of silicon, for example. The tabs and the leads are formed ofcopper alloy, for example. The wires 39 are aluminum wires or goldwires, for example. The solder 43 as die bond material is high-meltingpoint solder, for example. Resin paste may be used as die bond material,or Au—Si eutectic bonding may be used. The sealing resin for forming thesealing portion 44 is epoxy resin, for example.

Description will be given to the configuration of a semiconductor chipincorporated into the HSOP 46 in the first embodiment with reference toFIG. 9 and FIG. 10. Here, the configuration of a semiconductor chipincluding an nMISFET 33 will be described as an example.

As illustrated in FIG. 9, this semiconductor chip is formed by preparinga semiconductor substrate (hereafter, simply referred to as “substrate”)obtained by the following processing: an n⁻-type single-crystal siliconlayer 1B doped with impurity of n conductivity type is epitaxially grownover the surface of an n⁺-type single-crystal silicon substrate 1A of nconductivity type. This substrate includes: an active cell area ACA inwhich the active cell of a power MISFET is formed; an inactive cell areaNCA in which an inactive cell is formed; a gate wiring area GLA in whichwiring electrically connected with the gate electrode of the powerMISFET is formed; and a termination area FLR in which field limitingrings are formed. The n⁺-type single-crystal silicon substrate 1A andthe n⁻-type single-crystal silicon layer 1B form the drain region of thepower MISFET.

There are trenches 4 formed in the active cell area ACA and the inactivecell area NCA, and there is a trench 5 formed in the gate wiring areaGLA. The substrate is subjected to thermal oxidation, and a siliconoxide film 6 is formed on the side walls and bottom of the trenches 4and 5. This silicon oxide film 6 is the gate insulating film of thepower MISFET.

A field insulating film 3A is formed over the n⁻-type single-crystalsilicon layer 1B, and a silicon oxide film 9 is deposited over the film.

Further, contact grooves 15, 16, 17, and 18 are formed in an insulatingfilm 14, and a p⁺-type semiconductor region 20 is formed at the bottomof the contact grooves 15, 16, 17, and 18. This p⁺-type semiconductorregion 20 is for bringing the wiring into ohmic contact with p⁻-typesemiconductor regions 10 or p⁻-type field limiting rings 11 at thebottom of the contact grooves 15, 16, 17, and 18.

In the semiconductor chip, a thin TiW (titanium tungsten) film as abarrier conductor film is deposited over the insulating film 14including the interior of the contact grooves 15, 16, 17, 18, and 19 bysputtering, for example. Further, an Al (aluminum) film is formed overthe film. The barrier conductor film functions to prevent an undesiredreaction layer from being formed by contact between Al and the substrate(Si). The Al film means a film predominantly composed of Al, and it maycontain any other metal or the like.

The TiW film and the Al film are etched, and the following are formed: agate wiring 21 electrically connected with a gate lead-out electrode 8;a source pad (source electrode) 22 electrically connected with ann⁺-type semiconductor region 12 that forms the source region of thepower MISFET; and a wiring 23 that is electrically connected with one ofthe p⁻-type field limiting rings 11 and is electrically connected withthe source pad 22 in a region not shown in FIG. 9. Further, thefollowing are formed: a wiring 24 electrically connected with a p⁻-typefield limiting ring 11 that is different from the p⁻-type field limitingring 11 electrically connected with the wiring 23; a wiring 25electrically connected with an n⁺-type guard ring region 13; and a gatepad (gate electrode) electrically connected with the gate wiring 21.

When a plan view is drawn illustrating the way the gate wiring 21,source pad 22, wirings 23, 24, and 25, and gate pad are formed, that isas illustrated in FIG. 10. FIG. 10 illustrates a chip section CHPequivalent to one chip obtained by dividing a substrate into individualchips. The section illustrated in FIG. 9 shows the section of this chipsection taken along the line A-A.

In the chip section CHP (planar surface), as illustrate in FIG. 10, theactive cell area ACA, inactive cell area NCA, gate wiring area GLA, andtermination area FLR are so formed that the following is implemented:the inactive cell area NCA encircles the active cell area ACA; the gatewiring area GLA encircles the inactive cell area NCA; and thetermination area FLR encircles the gate wiring area GLA.

The n⁺-type semiconductor region 12 that forms the source of a powerMISFET in the first embodiment is formed in the active cell area ACA andis not formed in the inactive cell area NCA. In cases where the n⁺-typesemiconductor region 12 is also formed in the inactive cell area NCA, aparasitic MISFET is formed in which: the n⁺-type single-crystal siliconsubstrate 1A and the n⁻-type single crystal silicon layer 1B are a drainregion; the n⁺-type semiconductor region 12 is a source region; the gatelead-out electrode 8 is a gate electrode; and the p⁻-type semiconductorregions 10 are channels.

As mentioned above, the gate electrode 7 and the gate lead-out electrode8 are integrally formed and electrically connected with each other.Consequently, the following trouble can occur: when the power MISFET isoperated, this parasitic MISFET also operates, and electro-currentconstriction occurs in a cell in proximity to the peripheral area of thechip. To cope with this, the first embodiment adopts the followingconstruction: the power MISFET cell formed in the active cell area ACAis encircled with the inactive cell area NCA in which a dummy cell withno n⁺-type semiconductor region 12 present is formed. Thus, parasiticoperation due to such a parasitic MISFET can be prevented. The troubleof an occurrence of electro-current constriction in a cell in proximityto the peripheral area of the power MISFET chip can be therebyprevented.

As illustrated in FIG. 10, the planar pattern of gate electrodes 7(trenches 4) in the first embodiment is of rectangular mesh. The sourcepad 22 formed over the gate electrodes 7 is electrically connected withthe wiring 23. A gate pad (gate electrode) 26 is formed of the samewiring layer as the gate wiring 21, source pad 22, and wirings 23, 24,and 25 are, and is electrically connected with the gate wiring 21. Thewiring 25 electrically connected with the n⁺-type guard ring region 13and the wiring 24 and wiring 25 electrically connected with the p⁻-typefield limiting rings 11 are sequentially disposed from the outermostarea of the chip section so that the active cell area ACA is encircledwith them.

In the semiconductor device (HSOP 46) in the first embodiment, thefollowing is implemented in the HSOP 46 for driving a three-phase motor:a first semiconductor chip 30 including a PMISFET 32 and a secondsemiconductor chip 31 including an nMISFET 33 are mounted over each ofthe first tab 34, second tab 35, and third tab 36. The drains of thePMISFET 32 and nMISFET 33 over each tab are electrically connected witheach other. Thus, the HSOP 46 can be reduced in size.

More specific description will be given. Two of six semiconductor chipseach including MISFET are placed over each of three tabs divided incorrespondence with the number of phases of the motor 40. These chipsare packaged in one in a compact manner. This makes it possible toreduce the size of the semiconductor device (HSOP 46) for driving athree-phase motor, having a plurality of chips.

The respective back sides 34 b, 35 b, and 36 b of the first tab 34,second tab 35, and third tab 36 that also function as drain terminalsare exposed at the underside of the sealing portion 44. Further, eachtab is so formed that it is far thicker than the leads 37. Thus, eachtab can be provided with a heat sink function to enhance the heatradiating property of the HSOP 46.

As a result, the heat radiating property of the semiconductor device(HSOP 46) for driving a three-phase motor, having a plurality of chipscan be enhanced.

The HSOP 46 in the first embodiment is a semiconductor device of suchconstruction that p and nMISFETs are incorporated together. Descriptionwill be given to the effect obtained by this embodiment throughcomparison with the semiconductor device (HSOP 100) illustrated as acomparative example in FIG. 25. This semiconductor device has nMISFETsonly incorporated and is so constructed that a tab is divided into four.

In the above description, the drive circuit with p and nMISFETsincorporated together, illustrated in FIG. 4, was compared with thedrive circuit with nMISFETs only incorporated, illustrated as acomparative example in FIG. 5. As described through comparison, thedrive circuit with p and nMISFETs incorporated together has an advantagethat it can be operated with simpler circuitry.

The size of divided tabs is uniform in the HSOP 46 illustrated in FIG. 1as compared with that of the comparative example. Heat produced by eachtab is uniform, and this makes it possible to enhance the reliability ofthe system. Meanwhile, the HSOP 100 with nMISFETs only incorporated,illustrated as a comparative example in FIG. 25, involves the followingproblem. The common tab 50 for drain is much larger than the other tabs,and heat produced by each tab cannot be made uniform and the enhancementof reliability is difficult to accomplish.

In the HSOP 100 illustrated as a comparative example in FIG. 25, thesource electrodes of the high-side MISFETs and the drain electrodes ofthe low-side MISFETs are connected with each other through wires 39astride tabs. As a result, it is difficult to inspect erroneousconnection between tabs (due to sticking solder or the like). Whenvoltage is applied to between tabs in this case, any MISFET is almostshort-circuited, and lets a current through it. In the HSOP 46 in thefirst embodiment illustrated in FIG. 1, the individual tabs arecompletely separated from one another, and can be easily inspected forerroneous connection between tabs.

In the HSOP 100 illustrated as a comparative example in FIG. 25, wires39 are bonded to tabs, and thus bonding areas for wires 39 must beensured in the tabs. This imposes limitation on chip size. In case ofthe HSOP 46 in the first embodiment illustrated in FIG. 1, wires 39 arenot connected to tabs. Therefore, the chip size can be increased as longas the tab size permits. This is highly advantageous in terms ofcommercialization and assembling operation.

In the HSOP 100 illustrated as a comparative example in FIG. 25, wires39 are bonded astride tabs. Therefore, the switching noise of a low-sideMISFET gets into the source electrode of a high-side MISFET via theinductance of a wire 39, and shifts a potential. As a result, the riskthat its gate electrode is caused to malfunction is increased.

In case of the HSOP 46 in the first embodiment illustrated in FIG. 1,tabs are completely separated from one another. Therefore, they are notaffected by one another, and the reliability of the system can beenhanced.

Description will be given to the assembly of the HSOP 46 (semiconductordevice) in the first embodiment.

FIG. 11 and FIG. 12 illustrate the configuration of a substantial partof a lead frame 38 used in the assembly of the HSOP 46.

The lead frame 38 is provided in one package region with a first tab 34,second tab 35, and third tab 36, which are three tabs divided incorrespondence with the number of phases of the motor 40. A plurality ofleads 37 are provided around them. The first tab 34, second tab 35, andthird tab 36 are divided by slits 38 c formed between them.

Each of the plurality of leads 37 is supported by adjacent leads 37 anda dam bar 38 e, and of the plurality of leads 37, the leads 37 c fordrain are integrally joined with the respective tabs. More specificdescription will be given. Each tab is so constructed that a drainelectrode is shared between two semiconductor chips mounted over it.Therefore, the tabs are integrally joined with the leads 37 c for drainand supported by the leads 37 c for drain.

As illustrated in FIG. 12, each lead 37 c for drain is bent and providedwith a stepped portion 38 a. Thus, the wire bonding faces 37 d of theindividual leads 37, including the leads 37 c for drain, are so disposedthat they are farther from the tabs than the main surfaces 34 a, 35 a,and 36 a of the tabs on the main surface side. That is, the wire bondingfaces 37 d of the individual leads 37 are disposed at a higher levelthan the main surfaces 34 a, 35 a, and 36 a of the individual tabs are.

In the lead frame 38, the plurality of leads 37 and the first tab 34,second tab 35, and third tab 36 much thicker than the leads areintegrally formed. They are formed of one contour strip material ofcopper alloy, for example. The plate thickness of the leads 37 and thatof the tabs can be made different by metal rolling.

As illustrated in FIG. 13 and FIG. 14, V-grooves (groove portions) 34 c,35 c, and 36 c are formed at the respective peripheral areas of the mainsurfaces 34 a, 35 a, and 36 a of the first tab 34, second tab 35, andthird tab 36.

Second groove portions 38 b deeper than the V-grooves 34 c, 35 c, and 36c are formed in suspending portions 38 d that support the outer sideportions of the tabs positioned at both ends, of the three tabs.

As illustrated in FIG. 14, a protruding portion 38 f is formed on therespective side faces of the first tab 34, second tab 35, and third tab36 and in the second groove portions 38 b. The protruding portions 38 fcan be formed by crushing or the like.

As a method for varying the thickness of the tabs in the lead frame 38,the lead frame 38 may be formed of two frame materials, different inthickness, as illustrated as a modification in FIG. 15 and FIG. 16. Thatis, the following method may be adopted: the first tab 34, second tab35, and third tab 36 are formed using a thick plate material; the leadframe 38 is formed using a thin plate material, and then caulkingportions 38 h are formed by caulking to couple together each tab and thelead frame 38.

After the lead frame 38 illustrated in FIG. 11 is prepared, die bondingis carried out.

Here, the first semiconductor chips 30 and the second semiconductorchips 31 are mounted over the respective tabs with solder 43 in-between.At this time, of the six semiconductor chips, either the three firstsemiconductor chips 30 including a PMISFET 32 or the three secondsemiconductor chips 31 including an nMISFET 33 are continuouslydie-bonded. Then, the lead frame 38 is turned upside down, and the otherthree semiconductor chips are die-bonded.

As mentioned above, the V-grooves 34 c, 35 c, and 36 c are formed at theperipheral areas of the respective main surfaces 34 a, 35 a, and 36 a ofthe tabs. Therefore, solder 43 that is melted and runs off during diebonding can be prevented from flowing out by causing the solder 43 toflow into the V-grooves 34 c, 35 c, and 36 c.

After die bonding, wire bonding is carried out. The electrodes on themain surfaces 30 a and 31 a of the semiconductor chips and thecorresponding leads 37 are electrically connected with each otherthrough wires 39. At this time, the leads 37 are disposed at a higherlevel than the individual tabs as illustrated in FIG. 17. Thus, thewires 39 can be prevented from being brought into contact with an edgeof the main surface of a chip.

As a result, the wires 39 can be prevented from being short-circuited toa first semiconductor chip 30 or a second semiconductor chip 31.

Thereafter, plastic molding is carried out.

Here, using such sealing resin as epoxy resin, the semiconductor chips,the plurality of wires 39, and the like are plastic molded to form thesealing portion 44. At this time, plastic molding is carried out so thatthe back sides 34 b, 35 b, and 36 b of the individual tabs are exposedat the underside of the sealing portion 44 as illustrated in FIG. 7.

As mentioned above, the protruding portions 38 f are formed on the sidefaces of the first tab 34, second tab 35, and third tab 36 and in thesecond groove portions 38 b. Therefore, bonding power can be enhancedbetween the sealing resin and each tab.

Thereafter, the dam bars 38e in the lead frame 38 are cut to insulateeach lead 37 from the adjoining leads 37.

Thereafter, the outer leads 37 e are coated with solder plating 45 tofrom outer plating. The leads 37 are cut off from the frame portion 38 gof the lead frame 38, and the outer leads 37 e are bent and formed (intogull wing shape). This completes the assembly of the HSOP 46.

Second Embodiment

FIG. 19 is a plan view illustrating an example of the construction of asemiconductor device (with its tab divided into two and for driving asingle-phase motor) in a second embodiment of the invention as viewedthrough its sealing portion; FIG. 20 is a rear view illustrating anexample of the construction of the back side of the semiconductor deviceillustrated in FIG. 19, as applied to HSOP; and FIG. 21 is an equivalentcircuit diagram illustrating an example of the circuitry for driving asingle-phase motor in the semiconductor device illustrated in FIG. 19.

The semiconductor device in the second embodiment illustrated in FIG. 19is HSOP 47 for driving a single-phase motor, and two pMISFETs 32 and twonMISFETs 33 are incorporated into the device. FIG. 21 is a drawingillustrating an example of an equivalent circuit for driving asingle-phase motor. It has two pMISFETs 32 on the high side and twonMISFETs 33 on the low side, and drives a motor 40 in a single phase bythe four MISFETs in total. (Refer to FIG. 2 for the motor.)

In terms of circuitry, as illustrated in FIG. 19, the HSOP has two setsof circuits for driving, each set composed of a pMISFET 32 and annMISFET 33, and it drives the motor 40 in a single phase by thesecircuits. Therefore, the HSOP 47 in the second embodiment is also asemiconductor device with p and nMISFETs incorporated together.

The HSOP 47 has two divided tabs (first tab 34 and second tab 35), and aset of a pMISFET 32 and an nMISFFT 33 is mounted over each tab. Morespecific description will be given. A first semiconductor chip 30including a pMISFET 32 and a second semiconductor chip 31 including annMISFET 33 are mounted over the main surface 34 a of the first tab 34;and a first semiconductor chip 30 including a pMISFET 32 and a secondsemiconductor chip 31 including an nMISFET 33 are mounted over the mainsurface 35 a of the second tab 35.

At this time, the two first semiconductor chips 30 each including aPMISFET 32 are placed on the high side, and the two second semiconductorchips 31 each including an nMISFET 33 are placed on the low side.

The source pads 30 c formed over the main surfaces 30 a of the firstsemiconductor chips 30 are electrically connected with correspondingleads 37 b for source through conductive wire 39; the gate pads 30 dsimilarly formed are electrically connected with corresponding leads 37a for gate through conductive wires 39. The back sides of the firstsemiconductor chips 30 form drain electrodes, and these drain electrodesare electrically connected with the tabs with solder or the likein-between. The tabs and the leads 37 c for drain are integrally joinedwith each other.

Similarly, the source pads 31 c formed over the main surfaces 31 a ofthe second semiconductor chips 31 are electrically connected withcorresponding leads 37 b for source through conductive wires 39; thegate pads 31 d similarly formed are electrically connected withcorresponding leads 37 a for gate through conductive wires 39. The backsides of the second semiconductor chips 31 from drain electrodes, andthese drain electrodes are electrically connected with tabs with solderor the like in-between. The tabs and the leads 37 c for drain areintegrally joined with each other.

Therefore, the first semiconductor chip 30 and the second semiconductorchip 31 over the first tab 34 share a drain electrode between them overthe tab. The first semiconductor chip 30 and the second semiconductorchip 31 over the second tab 35 share a drain electrode between them overthe tab. That is, the first tab 34 and the second tab 35 arerespectively electrically connected with the drains of a PMISFET 32 andan nMISFET 33. The drains of the pMISFETs 32 and the nMISFETs 33 areelectrically connected with each other through each of the first tab 34and the second tab 35.

FIG. 19 illustrates the disposition (G, S, D) of the plurality of leads37 composed of leads 37 a for gate, leads 37 b for source, and leads 37c for drain as an example. However, the disposition of the leads is notlimited to that illustrated in FIG. 19.

The HSOP 47 has a sealing portion 44 that seals parts of the first tab34, second tab 35, and plural leads 37, the first semiconductor chips30, and the second semiconductor chips 31. As in the HSOP 46 in thefirst embodiment, also in the HSOP 47, the back sides 34 b and 35 b ofthe first tab 34 and the second tab 35 are exposed from the sealingportion 44 as illustrated in FIG. 20.

As in the HSOP 46 in the first embodiment, also in the HSOP 47, each ofthe first tab 34 and the second tab 35 is so formed that it is muchthicker than the leads 37.

In the semiconductor device (HSOP 47) in the second embodiment, thefollowing is implemented in the HSOP 47 for driving a single-phasemotor: a first semiconductor chip 30 including a PMISFET 32 and a secondsemiconductor chip 31 including an nMISFET 33 are mounted over each ofthe first tab 34 and the second tab 35. The drains of the pMISFET 32 andnMISFET 33 over each tab are electrically connected with each other.Thus, the HSOP 47 can be reduced in size. More specific description willbe given. Two of four semiconductor chips each including MISFET areplaced over each of two divided tabs, and these chips are packaged inone in a compact manner. This makes it possible to reduce the size ofthe HSOP 47 for driving a single-phase motor, having a plurality ofchips.

The respective back sides 34 b and 35 b of the first tab 34 and secondtab 35 that also function as drain terminals are exposed at theunderside of the sealing portion 44. Further, each tab is so formed thatit is thicker than the leads 37. Thus, each tab can be provided with aheat sink function to enhance the heat radiating property of the HSOP47.

As a result, the heat radiating property of the HSOP 47 for driving asingle-phase motor, having a plurality of chips can be enhanced.

Other effects obtained by the HSOP 47 are the same as by theabove-mentioned HSOP 46, and the repetitive description of them will beomitted.

Third Embodiment

FIG. 22 is a plan view illustrating an example of the construction of asemiconductor device (with its tab divided into four and for driving asingle-phase motor) in a third embodiment of the invention as viewedthrough its sealing portion; FIG. 23 is a rear view illustrating anexample of the construction of the back side of the semiconductor deviceillustrated in FIG. 22, as applied to HSOP; and FIG. 24 is an equivalentcircuit diagram illustrating an example of the circuitry for driving asingle-phase motor in the semiconductor device illustrated in FIG. 22.

As in the second embodiment, the semiconductor device in the thirdembodiment illustrated in FIG. 22 is HSOP 49 for driving a single-phasemotor, and two pMISFETs 32 and two nMISFETs 33 are incorporated into thedevice. FIG. 24 is a drawing illustrating an example of an equivalentcircuit for driving a single-phase motor. It has two pMISFETs 32 on thehigh side and two nMISFETs 33 on the low side, and drives a motor 40 ina single phase by the four MISFETs in total. (Refer to FIG. 2 for themotor.) In terms of circuitry, as illustrated in FIG. 22, the HSOP hasfour semiconductor chips individually mounted over different tabs. Thefour semiconductor chips are two first semiconductor chips 30 eachincluding a PMISFET 32 and two second semiconductor chips 31 eachincluding an nMISFET 33. The HSOP drives the motor 40 in a single phaseby these circuits. The HSOP 49 in the third embodiment is also asemiconductor device with p and nMISFETs incorporated together.

The HSOP 49 has four divided tabs (first tab 34, second tab 35, thirdtab 36, and fourth tab 48), and either a PMISFET 32 or an nMISFET 33 ismounted over each tab. The HSOP 49 in the third embodiment isconstructed as follows: first semiconductor chips 30 each including apMISFET 32 are mounted over the main surfaces 34 a and 35 a of the firsttab 34 and the second tab 35; and second semiconductor chips 31 eachincluding an nMISFET 33 are mounted over the main surfaces 36 a and 48 aof the third tab 36 and the fourth tab 48.

At this time, the four tabs are arranged in the order of first tab 34,third tab 36, second tab 35, and fourth tab 48 from either end. Sincethe pMISFETs 32 and the nMISFETs 33 are alternately placed, circuitconnection can be easily carried out with respect to the pMISFETs 32 andthe nMISFETs 33.

The source pads 30 c formed over the main surfaces 30 a of the firstsemiconductor chips 30 are electrically connected with correspondingleads 37 b for source through conductive wires 39; the gate pads 30 dsimilarly formed are electrically connected with corresponding leads 37a for gate through conductive wires 39. The back sides of the firstsemiconductor chips 30 form drain electrodes, and these drain electrodesare electrically connected with the tabs with solder or the likein-between. The tabs and the leads 37 c for drain are integrally joinedwith each other.

Similarly, the source pads 31 c formed over the main surfaces 31 a ofthe second semiconductor chips 31 are electrically connected withcorresponding leads 37 b for source through conductive wire 39; the gatepads 31 d similarly formed are electrically connected with correspondingleads 37 a for gate through conductive wire 39. The back sides of thesecond semiconductor chips 31 form drain electrodes, and these drainelectrodes are electrically connected with the tabs with solder or thelike in-between. The tabs and the leads 37 c for drain are integrallyjoined with each other.

FIG. 22 illustrates the disposition (G, S, D) of the plurality of leads37 composed of leads 37 a for gate, leads 37 b for source, and leads 37c for drain as an example. However, the disposition of the leads is notlimited to that illustrated in FIG. 22.

The HSOP 49 has a sealing portion 44 that seals parts of the first tab34, second tab 35, third tab 36, fourth tab 48, and plural leads 37, thefirst semiconductor chips 30, and the second semiconductor chips 31. Asin the HSOP 46 in the first embodiment, also in the HSOP 49, the backsides 34 b, 35 b, 36 b, and 48 b of the first tab 34, second tab 35,third tab 36, and fourth tab 48 are exposed from the sealing portion 44as illustrated in FIG. 23.

As in the HSOP 46 in the first embodiment, also in the HSOP 49, each ofthe first tab 34, second tab 35, third tab 36, and fourth tab 48 is soformed that it is much thicker than the leads 37.

In the semiconductor device (HSOP 49) in the third embodiment, thefollowing is implemented in the HSOP 49 for driving a single-phasemotor: either a first semiconductor chip 30 including a pMISFET 32 or asecond semiconductor chip 31 including an nMISFET 33 is mounted overeach of the first tab 34, second tab 35, third tab 36, and fourth tab48. Thus, the HSOP 49 can be reduced in size. More specific descriptionwill be given. Each of four semiconductor chips each including MISFET isplaced over each of four divided tabs, and these chips are packaged inone in a compact manner. This makes it possible to reduce the size ofthe HSOP 49 for driving a single-phase motor.

The respective back sides 34 b, 35 b, 36 b, and 48 b of the first tab34, second tab 35, third tab 36, and fourth tab 48 that also function asdrain terminals are exposed at the underside of the sealing portion 44.Further, each tab is so formed that it is thicker than the leads 37.Thus, each tab can be provided with a heat sink function to enhance theheat radiating property of the HSOP 49.

As a result, the heat radiating property of the HSOP 49 for driving asingle-phase motor, having a plurality of chips can be enhanced.

Other effects obtained by the HSOP 49 are the same as by theabove-mentioned HSOP 46, and the repetitive description of them will beomitted.

Up to this point, the invention made by the present inventors has beenconcretely described based on embodiments of the invention. However, theinvention is not limited to the above-mentioned embodiments, and variousmodifications can be made without departing from the scope of theinvention, needless to add.

An example will be taken. In the above description of the first, second,and third embodiments, the semiconductor device is HSOP with its outerleads 37 e bent and formed into gull wing shape. The semiconductordevice need not be HSOP, and it may be any other semiconductor device,such as SOJ (Small Outline J-leaded Package).

The invention is favorably applicable to an electronic device having aplurality of chips.

FIG. 1:

-   30/First semiconductor chip-   31/Second semiconductor chip-   34/First tab-   35/Second tab-   36/Third tab-   37/Lead-   44/Sealing portion-   46/HSOP (semiconductor device)    FIG. 2:-   41/Driver IC    FIG. 4:-   Motor    FIG. 5:-   101/Driver IC-   Motor    FIG. 7:-   34 b, 35 b, 36 b/Back side    FIG. 8:-   37 d/Wire bonding face    FIG. 9:-   Gate-   Source-   Drain    FIG. 13:-   34 c, 35 c, 36 c/V-groove (groove portion)    FIG. 14:-   34 a, 35 a, 36 a/Main surface-   38 f/Protruding portion    FIG. 18:-   Thermal resistance-   Time    FIG. 19:-   47/HSOP (semiconductor device)    FIG. 22:-   48/Fourth tab-   49/HSOP (semiconductor device)

1. A semiconductor device for driving a three-phase motor, comprising:first, second, and third tabs; a semiconductor chip including a pMISFETand a semiconductor chip including an nMISFET mounted over each of thefirst, second, and third tabs; a plurality of leads electricallyconnected with each of the semiconductor chips; and a sealing portionthat seals parts of the first, second, and third tab and the pluralityof leads and the semiconductor chips, wherein the drains of the pMISFETsand nMISFETs mounted over each of the first, second, and third tabs areelectrically connected with each other.
 2. The semiconductor deviceaccording to claim 1, wherein the first, second, and third tabs arerespectively electrically connected with the drains of the pMISFETs andnMISFETs.
 3. The semiconductor device according to claim 1, wherein therespective back sides of the first, second, and third tabs are exposedfrom the sealing portion.
 4. The semiconductor device according to claim1, wherein each of the thicknesses of the first, second, and third tabsis larger than the thickness of the leads.
 5. The semiconductor deviceaccording to claim 4, wherein the first, second, and third tabs areformed integrally with and joined with some of the plurality of leads.6. The semiconductor device according to claim 1, the breakdown voltagebetween the source and drain of the pMISFETs and nMISFETs is lower than100V.
 7. The semiconductor device according to claim 1, wherein a grooveportion is formed in the peripheral areas of the respective mainsurfaces of the first, second, and third tabs.
 8. The semiconductordevice according to claim 1, wherein a protruding portion is formed onthe respective side faces of the first, second, and third tabs.
 9. Thesemiconductor device according to claim 1, wherein the respective wirebonding faces of the plurality of leads are positioned farther from thefirst, second, and third tabs than the main surfaces of the individualtabs on the main surface side.
 10. A semiconductor device for driving asingle-phase motor, comprising: first and second tabs; a semiconductorchip including a pMISFET and a semiconductor chip including an nMISFETmounted over each of the first and second tabs; a plurality of leadselectrically connected with each of the semiconductor chips; and asealing portion that seals parts of the first and second tabs and theplurality of leads and the semiconductor chips, wherein the drains ofthe pMISFET and nMISFET mounted over each of the first and second tabsare electrically connected with each other.
 11. The semiconductor deviceaccording to claim 10, wherein the respective back sides of the firstand second tabs are exposed from the sealing portion.
 12. Thesemiconductor device according to claim 10, wherein each of thethicknesses of the first and second tabs is larger than the thickness ofthe leads. 13.-16. (canceled)